\XtoCVerification{uRateLimiter FiP16 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block uRateLimiter.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 266 \\ \hline
\textbf{CPU cycles} & 67 & 67 & 67 & 67 & ... & 90 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & 0 & -32768 & -31508 & -30247 & ... & -6554 \\ \hline
\textbf{Init (DSP)} & 0 & 9830 & 9830 & 9830 & ... & 9830 \\ \hline
\textbf{Enable (DSP)} & 0 & 0 & 0 & 0 & ... & 1 \\ \hline
\textbf{In} & 0 & -1 & -0.962 & -0.923 & ... & -0.2 \\ \hline
\textbf{Init} & 0 & 0.3 & 0.3 & 0.3 & ... & 0.3 \\ \hline
\textbf{Enable} & 0 & 0 & 0 & 0 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Parameters} \\ \hline
\textbf{Tr} & \SetCell[c=6]{c}0.001 \\ \hline
\textbf{Tf} & \SetCell[c=6]{c}0.003 \\ \hline
\textbf{ts\_fact} & \SetCell[c=6]{c}1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & -1 & -0.962 & -0.923 & ... & -0.2 \\ \hline
\textbf{Exp. Out} & 0 & -1 & -0.962 & -0.923 & ... & -0.2 \\ \hline
\textbf{Out (DSP)} & 0 & -32768 & -31508 & -30247 & ... & -6554 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & -32768 & -31508 & -30247 & ... & -6554 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$6,1035e-05 ($\pm$2 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 67 \\ \hline
Max CPU cycles & 158 \\ \hline
Avg CPU cycles & 89 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion test}{1}
Conversion test for General block uRateLimiter.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 37 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Mask parameters} \\ \hline
\textbf{Tr} & -10 & -9.444 & ... & 10 \\ \hline
\textbf{Tf} & -9 & -8.5 & ... & 9 \\ \hline
\textbf{ts\_fact} & 3 & 3 & ... & 3 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Controller parameters} \\ \hline
\textbf{RateUp} & 2147483647 & 2147483647 & ... & 64425 \\ \hline
\textbf{RateDown} & 2147483647 & 2147483647 & ... & 71583 \\ \hline
\textbf{Exp. RateUp} & 2147483647 & 2147483647 & ... & 64425 \\ \hline
\textbf{Exp. RateDown} & 2147483647 & 2147483647 & ... & 71583 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance RateUp & $\pm$0,0000e+00 \\ \hline
Tolerance RateDown & $\pm$0,0000e+00 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion-on-Target test}{1}
Conversion-on-Target test for General block uRateLimiter.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 37 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Mask parameters} \\ \hline
\textbf{Tr} & -10 & -9.444 & ... & 10 \\ \hline
\textbf{Tf} & -9 & -8.5 & ... & 9 \\ \hline
\textbf{ts\_fact} & 3 & 3 & ... & 3 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Controller parameters} \\ \hline
\textbf{RateUp} & 2147483647 & 2147483647 & ... & 64424 \\ \hline
\textbf{RateDown} & 2147483647 & 2147483647 & ... & 71582 \\ \hline
\textbf{Exp. RateUp} & 2147483647 & 2147483647 & ... & 64425 \\ \hline
\textbf{Exp. RateDown} & 2147483647 & 2147483647 & ... & 71583 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance RateUp & $\pm$1,0000e+00 \\ \hline
Tolerance RateDown & $\pm$1,0000e+00 \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 6095 \\ \hline
Max CPU cycles & 6408 \\ \hline
Avg CPU cycles & 6235 \\ \hline
\end{XtoCtabular}
