\XtoCVerification{uAdd FiP16 CPU TM4C123GH6}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & TM4C123GH6 \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for Math block uAdd.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 214 \\ \hline
\textbf{CPU cycles} & 25 & 25 & 25 & 25 & ... & 25 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{In1 (DSP)} & -32768 & -32150 & -31531 & -30913 & ... & 32767 \\ \hline
\textbf{In2 (DSP)} & 32767 & 32150 & 31531 & 30913 & ... & 32767 \\ \hline
\textbf{In1} & -1 & -0.981 & -0.962 & -0.943 & ... & 1 \\ \hline
\textbf{In2} & 1 & 0.981 & 0.962 & 0.943 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{Out} & -0 & 0 & 0 & 0 & ... & -0 \\ \hline
\textbf{Exp. Out} & 0 & 0 & 0 & 0 & ... & 0 \\ \hline
\textbf{Out (DSP)} & -1 & 0 & 0 & 0 & ... & -2 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 0 & 0 & 0 & ... & 0 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$6,1035e-05 ($\pm$2 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 25 \\ \hline
Max CPU cycles & 25 \\ \hline
Avg CPU cycles & 25 \\ \hline
\end{XtoCtabular}
