\XtoCVerification{uGain FiP32 CPU TMS320F28379D}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-22 \\
\textbf{Target controller} & TMS320F28379D \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block uGain.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 107 \\ \hline
\textbf{CPU cycles} & 42 & 42 & ... & 42 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & -2147483648 & -2106965089 & ... & 2147483647 \\ \hline
\textbf{In} & -1 & -0.981 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Parameters} \\ \hline
\textbf{Gain} & \SetCell[c=4]{c}2.1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & -0.1 & -0.06 & ... & 0.1 \\ \hline
\textbf{Exp. Out} & -0.1 & -0.06 & ... & 0.1 \\ \hline
\textbf{Out (DSP)} & -214748364 & -129659391 & ... & 214748361 \\ \hline
\textbf{Exp. Out (DSP)} & -214748365 & -129659390 & ... & 214748365 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$2,3283e-09 ($\pm$5 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 42 \\ \hline
Max CPU cycles & 42 \\ \hline
Avg CPU cycles & 42 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Parameter test}{1}
Parameter test for General block uGain.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 107 \\ \hline
\textbf{CPU cycles} & 42 & 42 & ... & 42 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & \SetCell[c=4]{c}858993459 \\ \hline
\textbf{In} & \SetCell[c=4]{c}0.4 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Parameters} \\ \hline
\textbf{Gain} & -3.7 & -3.63 & ... & 3.7 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0.52 & 0.548 & ... & -0.52 \\ \hline
\textbf{Exp. Out} & 0.52 & 0.548 & ... & -0.52 \\ \hline
\textbf{Out (DSP)} & 1116691498 & 1176658965 & ... & -1116691499 \\ \hline
\textbf{Exp. Out (DSP)} & 1116691497 & 1176658965 & ... & -1116691497 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$1,3970e-09 ($\pm$3 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 42 \\ \hline
Max CPU cycles & 42 \\ \hline
Avg CPU cycles & 42 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion test}{1}
Conversion test for General block uGain.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 37 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Mask parameters} \\ \hline
\textbf{Gain} & -10 & -9.444 & ... & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Controller parameters} \\ \hline
\textbf{V} & -1342177280 & -1267611876 & ... & 1342177280 \\ \hline
\textbf{sfr} & 27 & 27 & ... & 27 \\ \hline
\textbf{Exp. V} & -1342177280 & -1267611876 & ... & 1342177280 \\ \hline
\textbf{Exp. sfr} & 27 & 27 & ... & 27 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance V & $\pm$0,0000e+00 \\ \hline
Tolerance sfr & $\pm$0,0000e+00 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion-on-Target test}{1}
Conversion-on-Target test for General block uGain.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 37 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Mask parameters} \\ \hline
\textbf{Gain} & -10 & -9.444 & ... & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Controller parameters} \\ \hline
\textbf{V} & -1342177280 & -1267611904 & ... & 1342177280 \\ \hline
\textbf{sfr} & 27 & 27 & ... & 27 \\ \hline
\textbf{Exp. V} & -1342177280 & -1267611876 & ... & 1342177280 \\ \hline
\textbf{Exp. sfr} & 27 & 27 & ... & 27 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance V & $\pm$7,0000e+01 \\ \hline
Tolerance sfr & $\pm$0,0000e+00 \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 1228 \\ \hline
Max CPU cycles & 2972 \\ \hline
Avg CPU cycles & 2372 \\ \hline
\end{XtoCtabular}
