\XtoCVerification{Atan2 Float32 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for Math block Atan2.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 315 \\ \hline
\textbf{CPU cycles} & 135 & 145 & ... & 5077 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{y (DSP)} & 0 & 2 & ... & 0.166 \\ \hline
\textbf{x (DSP)} & 0 & 0 & ... & -1.993 \\ \hline
\textbf{y} & 0 & 2 & ... & 0.166 \\ \hline
\textbf{x} & 0 & 0 & ... & -1.993 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & 1.571 & ... & 3.058 \\ \hline
\textbf{Exp. Out} & 0 & 1.571 & ... & 3.058 \\ \hline
\textbf{Out (DSP)} & 0 & 1.571 & ... & 3.058 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 1.571 & ... & 3.058 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$2,5611e-07 ($\pm$550 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 135 \\ \hline
Max CPU cycles & 6555 \\ \hline
Avg CPU cycles & 4608 \\ \hline
\end{XtoCtabular}
