\XtoCVerification{Div FiP16 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for Math block Div.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 246 \\ \hline
\textbf{CPU cycles} & 88 & 106 & 103 & 113 & ... & 106 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{Num (DSP)} & 0 & 16384 & 0 & -32768 & ... & 32767 \\ \hline
\textbf{Den (DSP)} & 0 & 0 & 16384 & 32767 & ... & 32767 \\ \hline
\textbf{Num} & 0 & 0.5 & 0 & -1 & ... & 1 \\ \hline
\textbf{Den} & 0 & 0 & 0.5 & 1 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & 1 & 0 & -1 & ... & 1 \\ \hline
\textbf{Exp. Out} & 0 & 1 & 0 & -1 & ... & 1 \\ \hline
\textbf{Out (DSP)} & 0 & 32767 & 0 & -32767 & ... & 32767 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 32767 & 0 & -32768 & ... & 32767 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$1,2207e-04 ($\pm$4 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 88 \\ \hline
Max CPU cycles & 280 \\ \hline
Avg CPU cycles & 135 \\ \hline
\end{XtoCtabular}
