\XtoCVerification{SinGen FiP32 CPU dsPIC33EP256MC502}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & dsPIC33EP256MC502 \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block SinGen.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 200 \\ \hline
\textbf{CPU cycles} & 482 & 482 & ... & 482 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{A (DSP)} & 10737418 & 21474836 & ... & 2147483647 \\ \hline
\textbf{f (DSP)} & 2147483647 & 2147483647 & ... & 2147483647 \\ \hline
\textbf{A} & 0.005 & 0.01 & ... & 1 \\ \hline
\textbf{f} & 1 & 1 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Parameters} \\ \hline
\textbf{fmax} & \SetCell[c=4]{c}200 \\ \hline
\textbf{Offset} & \SetCell[c=4]{c}0.13 \\ \hline
\textbf{Phase} & \SetCell[c=4]{c}0 \\ \hline
\textbf{ts\_fact} & \SetCell[c=4]{c}1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{u} & 0.131 & 0.132 & ... & 0.13 \\ \hline
\textbf{Exp. u} & 0.131 & 0.132 & ... & 0.13 \\ \hline
\textbf{u (DSP)} & 280518584 & 284513150 & ... & 279172924 \\ \hline
\textbf{Exp. u (DSP)} & 280518630 & 284513449 & ... & 279172874 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance u & $\pm$6,9849e-05 ($\pm$150000 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 482 \\ \hline
Max CPU cycles & 496 \\ \hline
Avg CPU cycles & 489 \\ \hline
\end{XtoCtabular}
