\XtoCVerification{Int2Real FiP16\_Float32 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block Int2Real.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 113 \\ \hline
\textbf{CPU cycles} & 310 & 307 & ... & 307 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & -32768 & -32183 & ... & 32767 \\ \hline
\textbf{In} & -1 & -0.982 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Parameters} \\ \hline
\textbf{Scale} & \SetCell[c=4]{c}7.3 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & -7.3 & -7.17 & ... & 7.3 \\ \hline
\textbf{Exp. Out} & -7.3 & -7.17 & ... & 7.3 \\ \hline
\textbf{Out (DSP)} & -7.3 & -7.17 & ... & 7.3 \\ \hline
\textbf{Exp. Out (DSP)} & -7.3 & -7.17 & ... & 7.3 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$3,0518e-04 ($\pm$655360 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 207 \\ \hline
Max CPU cycles & 311 \\ \hline
Avg CPU cycles & 306 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Parameter test}{1}
Parameter test for General block Int2Real.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 15 \\ \hline
\textbf{CPU cycles} & 307 & 307 & ... & 307 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & \SetCell[c=4]{c}3277 \\ \hline
\textbf{In} & \SetCell[c=4]{c}0.1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Parameters} \\ \hline
\textbf{Scale} & -10 & -5 & ... & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & -1 & -0.5 & ... & 1 \\ \hline
\textbf{Exp. Out} & -1 & -0.5 & ... & 1 \\ \hline
\textbf{Out (DSP)} & -1 & -0.5 & ... & 1 \\ \hline
\textbf{Exp. Out (DSP)} & -1 & -0.5 & ... & 1 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$6,1035e-05 ($\pm$131072 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 256 \\ \hline
Max CPU cycles & 310 \\ \hline
Avg CPU cycles & 304 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion test}{1}
Conversion test for General block Int2Real.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 15 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Mask parameters} \\ \hline
\textbf{Scale} & -10 & -5 & ... & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Controller parameters} \\ \hline
\textbf{scale} & -0 & -0 & ... & 0 \\ \hline
\textbf{Exp. scale} & -0 & -0 & ... & 0 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance scale & $\pm$0,0000e+00 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion-on-Target test}{1}
Conversion-on-Target test for General block Int2Real.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 15 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Mask parameters} \\ \hline
\textbf{Scale} & -10 & -5 & ... & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Controller parameters} \\ \hline
\textbf{scale} & -0 & -0 & ... & 0 \\ \hline
\textbf{Exp. scale} & -0 & -0 & ... & 0 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance scale & $\pm$3,0000e-09 \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 829 \\ \hline
Max CPU cycles & 1075 \\ \hline
Avg CPU cycles & 1052 \\ \hline
\end{XtoCtabular}
