\XtoCVerification{uAdd FiP32 CPU TMS320F28379D}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-22 \\
\textbf{Target controller} & TMS320F28379D \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for Math block uAdd.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 214 \\ \hline
\textbf{CPU cycles} & 44 & 44 & ... & 44 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{In1 (DSP)} & -2147483648 & -2106965089 & ... & 2147483647 \\ \hline
\textbf{In2 (DSP)} & 2147483647 & 2106965089 & ... & 2147483647 \\ \hline
\textbf{In1} & -1 & -0.981 & ... & 1 \\ \hline
\textbf{In2} & 1 & 0.981 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & -0 & 0 & ... & -0 \\ \hline
\textbf{Exp. Out} & 0 & 0 & ... & 0 \\ \hline
\textbf{Out (DSP)} & -1 & 0 & ... & -2 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 0 & ... & 0 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$9,3132e-10 ($\pm$2 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 44 \\ \hline
Max CPU cycles & 44 \\ \hline
Avg CPU cycles & 44 \\ \hline
\end{XtoCtabular}
