\XtoCVerification{Atan2 FiP32 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for Math block Atan2.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 315 \\ \hline
\textbf{CPU cycles} & 88 & 441 & ... & 1101 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{y (DSP)} & 0 & 2147483647 & ... & 178433134 \\ \hline
\textbf{x (DSP)} & 0 & 0 & ... & -2140057858 \\ \hline
\textbf{y} & 0 & 1 & ... & 0.083 \\ \hline
\textbf{x} & 0 & 0 & ... & -0.997 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & 0.5 & ... & 0.973 \\ \hline
\textbf{Exp. Out} & 0 & 0.5 & ... & 0.974 \\ \hline
\textbf{Out (DSP)} & 0 & 1073741823 & ... & 2090479220 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 1073741824 & ... & 2090621061 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$6,5193e-04 ($\pm$1400000 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 88 \\ \hline
Max CPU cycles & 1229 \\ \hline
Avg CPU cycles & 797 \\ \hline
\end{XtoCtabular}
