\XtoCVerification{Atan2 FiP16 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for Math block Atan2.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 315 \\ \hline
\textbf{CPU cycles} & 94 & 161 & 177 & 168 & ... & 284 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{y (DSP)} & 0 & 32767 & -32768 & 0 & ... & 2723 \\ \hline
\textbf{x (DSP)} & 0 & 0 & 0 & 32767 & ... & -32655 \\ \hline
\textbf{y} & 0 & 1 & -1 & 0 & ... & 0.083 \\ \hline
\textbf{x} & 0 & 0 & 0 & 1 & ... & -0.997 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & 0.5 & -0.5 & 0 & ... & 0.973 \\ \hline
\textbf{Exp. Out} & 0 & 0.5 & -0.5 & 0 & ... & 0.974 \\ \hline
\textbf{Out (DSP)} & 0 & 16383 & -16385 & 0 & ... & 31898 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 16384 & -16384 & 0 & ... & 31900 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$7,6294e-04 ($\pm$25 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 94 \\ \hline
Max CPU cycles & 328 \\ \hline
Avg CPU cycles & 228 \\ \hline
\end{XtoCtabular}
