\XtoCVerification{Limitation FiP32 CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block Limitation.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=5]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & ... & 159 \\ \hline
\textbf{CPU cycles} & 60 & 60 & ... & 60 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & -2147483648 & -2064888123 & ... & 1288490189 \\ \hline
\textbf{max (DSP)} & 644245094 & 644245094 & ... & 2147483647 \\ \hline
\textbf{min (DSP)} & -858993459 & -858993459 & ... & -2147483648 \\ \hline
\textbf{In} & -1 & -0.962 & ... & 0.6 \\ \hline
\textbf{max} & 0.3 & 0.3 & ... & 1 \\ \hline
\textbf{min} & -0.4 & -0.4 & ... & -1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=5]{l} \textit{Outputs} \\ \hline
\textbf{Out} & -0.4 & -0.4 & ... & 0.6 \\ \hline
\textbf{Exp. Out} & -0.4 & -0.4 & ... & 0.6 \\ \hline
\textbf{Out (DSP)} & -858993459 & -858993459 & ... & 1288490189 \\ \hline
\textbf{Exp. Out (DSP)} & -858993459 & -858993459 & ... & 1288490189 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$4,6566e-10 ($\pm$1 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 57 \\ \hline
Max CPU cycles & 60 \\ \hline
Avg CPU cycles & 58 \\ \hline
\end{XtoCtabular}
