\XtoCVerification{Sequencer Bool CPU STM32F072RB}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & STM32F072RB \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block Sequencer.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 16 \\ \hline
\textbf{CPU cycles} & 77 & 100 & 120 & 120 & ... & 77 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{Start (DSP)} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\textbf{Start} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Parameters} \\ \hline
\textbf{Delay1} & \SetCell[c=6]{c}0 \\ \hline
\textbf{Delay2} & \SetCell[c=6]{c}0 \\ \hline
\textbf{Delay3} & \SetCell[c=6]{c}0.001 \\ \hline
\textbf{Delay4} & \SetCell[c=6]{c}0 \\ \hline
\textbf{ts\_fact} & \SetCell[c=6]{c}1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{Out1} & 0 & 0 & 1 & 1 & ... & 0 \\ \hline
\textbf{Out2} & 0 & 0 & 0 & 1 & ... & 0 \\ \hline
\textbf{Out3} & 0 & 0 & 0 & 0 & ... & 0 \\ \hline
\textbf{Out4} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out1} & 0 & 0 & 1 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out2} & 0 & 0 & 0 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out3} & 0 & 0 & 0 & 0 & ... & 0 \\ \hline
\textbf{Exp. Out4} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\textbf{Out1 (DSP)} & 0 & 0 & 1 & 1 & ... & 0 \\ \hline
\textbf{Out2 (DSP)} & 0 & 0 & 0 & 1 & ... & 0 \\ \hline
\textbf{Out3 (DSP)} & 0 & 0 & 0 & 0 & ... & 0 \\ \hline
\textbf{Out4 (DSP)} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out1 (DSP)} & 0 & 0 & 1 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out2 (DSP)} & 0 & 0 & 0 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out3 (DSP)} & 0 & 0 & 0 & 0 & ... & 0 \\ \hline
\textbf{Exp. Out4 (DSP)} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out1 & $\pm$0,0000e+00 ($\pm$0 LSB) \\ \hline
Tolerance Out2 & $\pm$0,0000e+00 ($\pm$0 LSB) \\ \hline
Tolerance Out3 & $\pm$0,0000e+00 ($\pm$0 LSB) \\ \hline
Tolerance Out4 & $\pm$0,0000e+00 ($\pm$0 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 77 \\ \hline
Max CPU cycles & 120 \\ \hline
Avg CPU cycles & 113 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion test}{1}
Conversion test for General block Sequencer.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|X[c]|X[c]|X[c]|}}
\hline
\SetRow{lightgray} \SetCell[c=4]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 \\ \hline
\SetRow{lightgray!50} \SetCell[c=4]{l} \textit{Mask parameters} \\ \hline
\textbf{Delay1} & 0.1 & 0.1 & 0.1 \\ \hline
\textbf{Delay2} & 0.2 & 0.2 & 0.2 \\ \hline
\textbf{Delay3} & 1 & 1 & 1 \\ \hline
\textbf{Delay4} & 1.7 & 1.7 & 1.7 \\ \hline
\textbf{ts\_fact} & 1 & 2 & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=4]{l} \textit{Controller parameters} \\ \hline
\textbf{delay3} & 10000 & 5000 & 1000 \\ \hline
\textbf{delay4} & 17000 & 8500 & 1700 \\ \hline
\textbf{delay1} & 1000 & 500 & 100 \\ \hline
\textbf{delay2} & 2000 & 1000 & 200 \\ \hline
\textbf{Exp. delay3} & 10000 & 5000 & 1000 \\ \hline
\textbf{Exp. delay4} & 17000 & 8500 & 1700 \\ \hline
\textbf{Exp. delay1} & 1000 & 500 & 100 \\ \hline
\textbf{Exp. delay2} & 2000 & 1000 & 200 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance delay3 & $\pm$0,0000e+00 \\ \hline
Tolerance delay4 & $\pm$0,0000e+00 \\ \hline
Tolerance delay1 & $\pm$0,0000e+00 \\ \hline
Tolerance delay2 & $\pm$0,0000e+00 \\ \hline
\end{XtoCtabular}
\XtoCTestCase{Conversion-on-Target test}{1}
Conversion-on-Target test for General block Sequencer.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|X[c]|X[c]|X[c]|}}
\hline
\SetRow{lightgray} \SetCell[c=4]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 \\ \hline
\SetRow{lightgray!50} \SetCell[c=4]{l} \textit{Mask parameters} \\ \hline
\textbf{Delay1} & 0.1 & 0.1 & 0.1 \\ \hline
\textbf{Delay2} & 0.2 & 0.2 & 0.2 \\ \hline
\textbf{Delay3} & 1 & 1 & 1 \\ \hline
\textbf{Delay4} & 1.7 & 1.7 & 1.7 \\ \hline
\textbf{ts\_fact} & 1 & 2 & 10 \\ \hline
\SetRow{lightgray!50} \SetCell[c=4]{l} \textit{Controller parameters} \\ \hline
\textbf{delay3} & 10000 & 5000 & 1000 \\ \hline
\textbf{delay4} & 17000 & 8500 & 1700 \\ \hline
\textbf{delay1} & 1000 & 500 & 100 \\ \hline
\textbf{delay2} & 2000 & 1000 & 200 \\ \hline
\textbf{Exp. delay3} & 10000 & 5000 & 1000 \\ \hline
\textbf{Exp. delay4} & 17000 & 8500 & 1700 \\ \hline
\textbf{Exp. delay1} & 1000 & 500 & 100 \\ \hline
\textbf{Exp. delay2} & 2000 & 1000 & 200 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance delay3 & $\pm$0,0000e+00 \\ \hline
Tolerance delay4 & $\pm$0,0000e+00 \\ \hline
Tolerance delay1 & $\pm$0,0000e+00 \\ \hline
Tolerance delay2 & $\pm$0,0000e+00 \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 5808 \\ \hline
Max CPU cycles & 5817 \\ \hline
Avg CPU cycles & 5814 \\ \hline
\end{XtoCtabular}
