\XtoCVerification{LoopBreaker FiP16 CPU TM4C123GH6}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & TM4C123GH6 \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block LoopBreaker.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 18 \\ \hline
\textbf{CPU cycles} & 23 & 23 & 23 & 23 & ... & 23 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & 0 & 32767 & 32767 & 32767 & ... & 0 \\ \hline
\textbf{In} & 0 & 1 & 1 & 1.1 & ... & 0 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\textbf{Exp. Out} & 0 & 1 & 1 & 1 & ... & 0 \\ \hline
\textbf{Out (DSP)} & 0 & 32767 & 32767 & 32767 & ... & 0 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 32767 & 32767 & 32767 & ... & 0 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$3,0518e-05 ($\pm$1 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 23 \\ \hline
Max CPU cycles & 23 \\ \hline
Avg CPU cycles & 23 \\ \hline
\end{XtoCtabular}
