\XtoCVerification{TypeConv Bool\_FiP16 CPU TMS320F28379D}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-22 \\
\textbf{Target controller} & TMS320F28379D \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block TypeConv.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|X[c]|X[c]|}}
\hline
\SetRow{lightgray} \SetCell[c=3]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 \\ \hline
\textbf{CPU cycles} & 40 & 46 \\ \hline
\SetRow{lightgray!50} \SetCell[c=3]{l} \textit{Inputs} \\ \hline
\textbf{In (DSP)} & 0 & 1 \\ \hline
\textbf{In} & 0 & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=3]{l} \textit{Outputs} \\ \hline
\textbf{Out} & 0 & 1 \\ \hline
\textbf{Exp. Out} & 0 & 1 \\ \hline
\textbf{Out (DSP)} & 0 & 32767 \\ \hline
\textbf{Exp. Out (DSP)} & 0 & 32767 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance Out & $\pm$0,0000e+00 ($\pm$0 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 40 \\ \hline
Max CPU cycles & 46 \\ \hline
Avg CPU cycles & 43 \\ \hline
\end{XtoCtabular}
