\XtoCVerification{SinGen FiP16 CPU TMS320F28335}
\begin{tabular}{l l}
\textbf{Date of Test} & 2026-06-19 \\
\textbf{Target controller} & TMS320F28335 \\
\end{tabular}
\vspace{1ex}
\XtoCTestCase{Inport test}{1}
Inport test for General block SinGen.

\vspace{1em}
\begin{tblr}{width=\textwidth, colspec={|c|c|c|c|c|X[c]|c|}}
\hline
\SetRow{lightgray} \SetCell[c=7]{l} \textbf{Test results} \\ \hline
\textbf{Time step} & 1 & 2 & 3 & 4 & ... & 200 \\ \hline
\textbf{CPU cycles} & 117 & 117 & 117 & 117 & ... & 117 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Inputs} \\ \hline
\textbf{A (DSP)} & 164 & 328 & 492 & 655 & ... & 32767 \\ \hline
\textbf{f (DSP)} & 32767 & 32767 & 32767 & 32767 & ... & 32767 \\ \hline
\textbf{A} & 0.005 & 0.01 & 0.015 & 0.02 & ... & 1 \\ \hline
\textbf{f} & 1 & 1 & 1 & 1 & ... & 1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Parameters} \\ \hline
\textbf{fmax} & \SetCell[c=6]{c}200 \\ \hline
\textbf{Offset} & \SetCell[c=6]{c}0.13 \\ \hline
\textbf{Phase} & \SetCell[c=6]{c}0 \\ \hline
\textbf{ts\_fact} & \SetCell[c=6]{c}1 \\ \hline
\SetRow{lightgray!50} \SetCell[c=7]{l} \textit{Outputs} \\ \hline
\textbf{u} & 0.131 & 0.133 & 0.136 & 0.14 & ... & 0.135 \\ \hline
\textbf{Exp. u} & 0.131 & 0.132 & 0.136 & 0.14 & ... & 0.13 \\ \hline
\textbf{u (DSP)} & 4281 & 4342 & 4441 & 4576 & ... & 4435 \\ \hline
\textbf{Exp. u (DSP)} & 4280 & 4341 & 4441 & 4576 & ... & 4260 \\ \hline
\end{tblr}
\vspace{1ex}

\begin{XtoCtabular}{Test settings}
Tolerance u & $\pm$5,3711e-03 ($\pm$176 LSB) \\ \hline
\end{XtoCtabular}

\begin{XtoCtabular}{Test statistics}
Min CPU cycles & 117 \\ \hline
Max CPU cycles & 117 \\ \hline
Avg CPU cycles & 117 \\ \hline
\end{XtoCtabular}
