/**
 * @file cpu_ctrl_xmc4.c
 * @date 2015-08-31
 * NOTE:
 * This file is generated by DAVE. Any manual modification done to this file will be lost when the code is regenerated.
 */
/**
 * @cond
 ***********************************************************************************************************************
 * CPU_CTRL_XMC4 v4.0.14 - Sets the priority grouping for NVIC
 *
 * Copyright (c) 2015-2016, Infineon Technologies AG
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
 * following conditions are met:
 *
 *   Redistributions of source code must retain the above copyright notice, this list of conditions and the  following
 *   disclaimer.
 *
 *   Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
 *   following disclaimer in the documentation and/or other materials provided with the distribution.
 *
 *   Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
 *   products derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  OF THE
 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes
 * with Infineon Technologies AG (dave@infineon.com).
 ***********************************************************************************************************************
 *
 * Change History
 * --------------
 *
 * 2015-02-16:
 *     - Initial version<br>
 *
 * 2015-08-31:
 *     - Added hard fault handler
 *     - Added CPU_CTRL_XMC4_MPU_Enable, CPU_CTRL_XMC4_MPU_Disable APIs
 *
 * 2016-11-29:
 *     - Changed hard fault handler to avoid reading from the stack in case an stack overflow caused the fault.
 *
 * @endcond
 *
 */
/***********************************************************************************************************************
 * HEADER FILES
 **********************************************************************************************************************/
#include "cpu_ctrl_xmc4.h"
/***********************************************************************************************************************
 * MACROS
 **********************************************************************************************************************/

/***********************************************************************************************************************
 * LOCAL DATA
 **********************************************************************************************************************/

/***********************************************************************************************************************
 * LOCAL ROUTINES
 **********************************************************************************************************************/

/**********************************************************************************************************************
* API IMPLEMENTATION
**********************************************************************************************************************/
/*
 * API to retrieve the version of the CPU_CTRL_XMC4 APP
 */
DAVE_APP_VERSION_t CPU_CTRL_XMC4_GetAppVersion(void)
{
  DAVE_APP_VERSION_t version;

  version.major = CPU_CTRL_XMC4_MAJOR_VERSION;
  version.minor = CPU_CTRL_XMC4_MINOR_VERSION;
  version.patch = CPU_CTRL_XMC4_PATCH_VERSION;

  return (version);
}
/* Dummy Init API to maintain backward compatibility */
CPU_CTRL_XMC4_STATUS_t CPU_CTRL_XMC4_Init(CPU_CTRL_XMC4_t *const handler)
{
  (void)handler;
  return CPU_CTRL_XMC4_STATUS_SUCCESS;
}

/*
 * API to enable the MPU
 */
void CPU_CTRL_XMC4_MPU_Enable(uint32_t options)
{
  MPU->CTRL = MPU_CTRL_ENABLE_Msk | options;
  __DSB(); /* Ensure MPU settings take effect */
  __ISB(); /* Sequence instruction fetches using updated settings */
}

/*
 * API to disable the MPU
 */
void CPU_CTRL_XMC4_MPU_Disable(void)
{
  __DMB(); /* make sure all transfers are done */
  MPU->CTRL = 0;
}

#if (HARDFAULT_ENABLED == 1)

volatile uint32_t stacked_r0;
volatile uint32_t stacked_r1;
volatile uint32_t stacked_r2;
volatile uint32_t stacked_r3;
volatile uint32_t stacked_r12;
volatile uint32_t stacked_lr;
volatile uint32_t stacked_pc;
volatile uint32_t stacked_psr;
volatile uint32_t _CFSR;
volatile uint32_t _HFSR;
volatile uint32_t _DFSR;
volatile uint32_t _AFSR;
volatile uint32_t _BFAR;
volatile uint32_t _MMAR;

/**
 * This is called from the HardFault_Handler with a pointer the Fault stack
 * as the parameter. We can then read the values from the stack and place them
 * into local variables for ease of reading.
 * We then read the various Fault Status and Address Registers to help decode
 * cause of the fault.
 * The function ends with a BKPT instruction to force control back into the debugger
 * Original code from http://www.support.code-red-tech.com/CodeRedWiki/DebugHardFault
 */
#if defined(__GNUC__)
#pragma GCC diagnostic ignored "-Wunused-but-set-variable"
#endif
__attribute__((naked)) void __HardFault_Handler(uint32_t args[])
{

  // Configurable Fault Status Register
  // Consists of MMSR, BFSR and UFSR
  _CFSR = SCB->CFSR;

  // Hard Fault Status Register
  _HFSR = SCB->HFSR;

  // Debug Fault Status Register
  _DFSR = SCB->DFSR;

  // Auxiliary Fault Status Register
  _AFSR = SCB->AFSR;

  // Read the Fault Address Registers. These may not contain valid values.
  // Check BFARVALID/MMARVALID to see if they are valid values
  // MemManage Fault Address Register
  _MMAR = SCB->MMFAR;

  // Bus Fault Address Register
  _BFAR = SCB->BFAR;

  stacked_r0 = ((uint32_t)args[0]);
  stacked_r1 = ((uint32_t)args[1]);
  stacked_r2 = ((uint32_t)args[2]);
  stacked_r3 = ((uint32_t)args[3]);
  stacked_r12 = ((uint32_t)args[4]);
  stacked_lr = ((uint32_t)args[5]);
  stacked_pc = ((uint32_t)args[6]);
  stacked_psr = ((uint32_t)args[7]);

  __asm("BKPT 0\n") ; // Break into the debugger

}


/*KEIL*/
#if defined(__CC_ARM)
__asm void HardFault_Handler(void)
{
  EXTERN __HardFault_Handler [CODE]

  TST    LR, #4
  ITE    EQ
  MRSEQ  R0, MSP
  MRSNE  R0, PSP
  B      __HardFault_Handler
}
#endif

/*IAR*/
#if defined(__ICCARM__)
void HardFault_Handler(void)
{
  asm("  TST    LR, #4  \n"
	  "  ITE    EQ  \n"
	  "  MRSEQ  R0, MSP \n"
	  "  MRSNE  R0, PSP \n"
	  "  B      __HardFault_Handler\n");
}
#endif

/*TASKING*/
#if defined(__TASKING__)
void HardFault_Handler(void)
{
__asm("  TST    LR, #4  \n"
      "  ITE    EQ  \n"
      "  MRSEQ  R0, MSP \n"
      "  MRSNE  R0, PSP \n"
      "  B      __HardFault_Handler\n");
}

#endif

/*GCC*/
#if defined(__GNUC__)
__attribute__((naked)) void HardFault_Handler(void)
{
__asm("  TST    LR, #4  \n"
      "  ITE    EQ  \n"
      "  MRSEQ  R0, MSP \n"
      "  MRSNE  R0, PSP \n"
      "  B      __HardFault_Handler\n");
}
#endif
#endif
